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ARM: 8661/1: dts: r7s72100: add l2 cache
authorChris Brandt <chris.brandt@renesas.com>
Thu, 16 Feb 2017 17:55:55 +0000 (18:55 +0100)
committerRussell King <rmk+kernel@armlinux.org.uk>
Fri, 17 Mar 2017 10:01:28 +0000 (10:01 +0000)
commitf08578e6da96043ec07a695fb6f4cba27a9d22d7
tree6337728f202b5b2fafcea8ebf497afe708f4fc8atree | snapshot (tar.gz zip)
parenta96bb197693eb9e7a7221867bd944ccd6b6e12e6commit | diff
ARM: 8661/1: dts: r7s72100: add l2 cache

Note that early-bresp-disable and full-line-zero-disable are required
because the sideband signals between the CPU and L2C were not connected
in this SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
arch/arm/boot/dts/r7s72100.dtsi diff | blob | blame | history