drm/i915: Fix the interlace mode selection for gmch platforms
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 28 Mar 2014 21:29:31 +0000 (23:29 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 31 Mar 2014 08:46:32 +0000 (10:46 +0200)
commitefc2cfff28a9424a0f9f8b068c6c8697435664c3
tree51ab2160920e3df0fd24cd3f9cf086146d5013c9
parent609aeacaacd9db3d7abb2eb4d2ff8e62af8ce283
drm/i915: Fix the interlace mode selection for gmch platforms

PIPECONF_INTERLACE_W_FIELD_INDICATION is only meant to be used for sdvo
since it implies a slightly weird vsync shift of htotal/2. For everything
else we should use PIPECONF_INTERLACE_W_SYNC_SHIFT and let the value in
the VSYNCSHIFT register take effect.

The only exception is gen3 simply because VSYNCSHIFT didn't exist yet.
Gen2 doesn't support interlaced modes at all, so we can drop the
explicit gen2 checks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c