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drm/i915/skl: Adjust the port PLL selection code
authorSatheeshakrishna M <satheeshakrishna.m@intel.com>
Thu, 13 Nov 2014 14:55:19 +0000 (14:55 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 14 Nov 2014 10:18:46 +0000 (11:18 +0100)
commitefa80add54d12bdeba996220463b6ee4ff6b81ae
tree9f2515d34f39ea77ee237e55f7bf02dc83d36c5ctree | snapshot (tar.gz zip)
parentd1a2dc7835f1258ac91cbdd8da1bc97b029b80f7commit | diff
drm/i915/skl: Adjust the port PLL selection code

Skylake deprecates the usage of PORT_CLK_SEL and we are advised to use
the new DPLL_CRTL2 for the DDI->PLL mapping.

v2: Modified as per review comments

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ddi.c diff | blob | blame | history