drm/i915/cnl: Implement .set_cdclk() for CNL
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 9 Jun 2017 22:25:59 +0000 (15:25 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Mon, 12 Jun 2017 16:40:54 +0000 (09:40 -0700)
commitef4f7a689ac5f61e36ac9ae77ac967b6469ae68b
tree1a283727176b0091eb104862e7c86c28d64fbaab
parent945f2672ccbb5c92a8a7bf23cba3a68a6b0885e7
drm/i915/cnl: Implement .set_cdclk() for CNL

Add support for changing the cdclk frequency on CNL. Again, quite
similar to BXT, but there are some annoying differences which means
trying to share more code might not be feasible:
* PLL ratio now lives in the PLL enable register
* pcode came from SKL, not from BXT

We support three cdclk frequencies: 168,336,528 Mhz. The first two
use the same PLL frequency, the last one uses a different one meaning
we once again may need to toggle the PLL off and on when changing
cdclk.

v2: Rebased by Rodrigo on top of Ville's cdclk rework.
v3: Respect order of set_ bellow get_ (Ville)
v4: Added __attribute__((unused)) to avoid broken compilation with Werror.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-2-git-send-email-rodrigo.vivi@intel.com
drivers/gpu/drm/i915/intel_cdclk.c