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(parent: 11ff376) | patch
clk: rockchip: fix rk3288 pll status register location
authorJianqun <jay.xu@rock-chips.com>
Mon, 1 Sep 2014 21:56:28 +0000 (23:56 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 27 Sep 2014 15:57:10 +0000 (17:57 +0200)
commitee17eb83c48e04653d8b430735f82fd4cdac6ca3
tree1d35ef5ad89f6671ad59a4a9cfe01f8621ddbb6dtree | snapshot (tar.gz zip)
parent11ff376fcfc0135b8947d27ab80162c218d1af90commit | diff
clk: rockchip: fix rk3288 pll status register location

In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
drivers/clk/rockchip/clk-rk3288.c diff | blob | blame | history