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(parent: f114040) | patch
spi: cadence: Fix 3-to-8 mux mode
authorLars-Peter Clausen <lars@metafoo.de>
Thu, 27 Nov 2014 15:12:18 +0000 (16:12 +0100)
committerMark Brown <broonie@kernel.org>
Fri, 28 Nov 2014 11:42:11 +0000 (11:42 +0000)
commitee0ebe81004bd0bedf7abe8a2f3eb745da0264dc
treee70b68a84922836fc2154bf4f4703e3e6a5f0c35tree | snapshot (tar.gz zip)
parentf114040e3ea6e07372334ade75d1ee0775c355e1commit | diff
spi: cadence: Fix 3-to-8 mux mode

In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
control register. Currently the driver never sets this bit even when
configured for 3-to-8 mux mode. This patch adds code which sets the bit
during device initialization when necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-cadence.c diff | blob | blame | history