clk: rockchip: fix up the pll clks error for rv1108 SoC
authorElaine Zhang <zhangqing@rock-chips.com>
Wed, 2 Aug 2017 08:33:04 +0000 (16:33 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 7 Aug 2017 22:48:53 +0000 (00:48 +0200)
commiteca05f0011de16f7a889e14dc36c7618d040884a
treee9a83bf0c753283ac79129f48c3b62b5c2ae9e0c
parentd00b4d943d8c2372a01533b1af3d49c126a5a415
clk: rockchip: fix up the pll clks error for rv1108 SoC

fix up the lock_shift describe error.
remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rv1108.c