coresight tmc etr: Setup AXI cache encoding for read transfers
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Wed, 2 Aug 2017 16:22:15 +0000 (10:22 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 28 Aug 2017 14:05:49 +0000 (16:05 +0200)
commitebab6a7db2c599b5c29d033f3a20f86016d9a9b8
treee366e6fdf34fdef7c5c530a4f96c1636ef3f85cf
parentcd407abd5efd6f36b6372d615fbab486936e90f4
coresight tmc etr: Setup AXI cache encoding for read transfers

If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/hwtracing/coresight/coresight-tmc-etr.c
drivers/hwtracing/coresight/coresight-tmc.h