PCI: Fix PCIe capability sizes
authorAlex Williamson <alex.williamson@redhat.com>
Thu, 10 Aug 2017 16:54:31 +0000 (10:54 -0600)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 24 Aug 2017 16:24:59 +0000 (11:24 -0500)
commitea5311c7e752dbec9bfbdd79992a8772b37f32fa
treef6a4786b3e76973a8e8af0badea39100aeaf1aca
parentb63773a801ff7f7f047894a9be23616f4491aca8
PCI: Fix PCIe capability sizes

PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 defines the size of the PCIe capability
structure for v1 devices with link, but we also have a need in the vfio
code for sizing the capability for devices without link, such as Root
Complex Integrated Endpoints.  Create a separate define for this ending the
structure before the link fields.

Additionally, this reveals that PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 is currently
incorrect, ending the capability length before the v2 link fields.  Rename
this to specify an RC Integrated Endpoint (no link) capability length and
move PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to include the link fields as we have
for the v1 version.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
[bhelgaas: add "_" in "PCI_CAP_EXP_RC ENDPOINT_SIZEOF_V2 44"]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
include/uapi/linux/pci_regs.h