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(parent: 8a57d27) | patch
drm/nv44/vm: fix and enable use of "real" pciegart
authorBen Skeggs <bskeggs@redhat.com>
Wed, 26 Sep 2012 22:55:53 +0000 (08:55 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 3 Oct 2012 03:13:17 +0000 (13:13 +1000)
commite5f186c4f9812eccbc291da6dfe8b15da546f961
tree84e667ebbe00bd91e10cff16defaad95b38d85a9tree | snapshot (tar.gz zip)
parent8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8commit | diff
drm/nv44/vm: fix and enable use of "real" pciegart

Something seems to be missing in regards to flushing specific ranges of
the TLB.  For the moment, flushing the entire thing seems to make it
work alright.

Should give 39-bit DMA addressing on the relevant chipsets.

v2: allocate contig 16KiB for dummy pages, reported by mwk on irc

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/subdev/device/nv40.c diff | blob | blame | history
drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c diff | blob | blame | history
drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h diff | blob | blame | history
drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c diff | blob | blame | history
Motorola kernel-slsi