drm/i915: Treat WC a separate cache domain
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 12 Apr 2017 11:01:11 +0000 (12:01 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 12 Apr 2017 11:35:17 +0000 (12:35 +0100)
commite22d8e3c69a9f432b40baaaf3f894a128fdc2222
treef076dadac5c963736a8fe1a25d31013f512d0366
parentef74921bc679232c6590afa881d3ea605ebdddd8
drm/i915: Treat WC a separate cache domain

When discussing a new WC mmap, we based the interface upon the
assumption that GTT was fully coherent. How naive! Commits 3b5724d702ef
("drm/i915: Wait for writes through the GTT to land before reading
back") and ed4596ea992d ("drm/i915/guc: WA to address the Ringbuffer
coherency issue") demonstrate that writes through the GTT are indeed
delayed and may be overtaken by direct WC access. To be safe, if
userspace is mixing WC mmaps with other potential GTT access (pwrite,
GTT mmaps) it should use set_domain(WC).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96563
Testcase: igt/gem_pwrite/small-gtt*
Testcase: igt/drv_selftest/coherency
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170412110111.26626-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/intel_guc_log.c
drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
drivers/gpu/drm/i915/selftests/i915_gem_request.c
include/uapi/drm/i915_drm.h