drm/i915: Clear PCODE_DATA1 on SNB+
authorDamien Lespiau <damien.lespiau@intel.com>
Thu, 13 Nov 2014 17:51:50 +0000 (17:51 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 14 Nov 2014 10:29:12 +0000 (11:29 +0100)
commitdddab346d8285428ddfeab25c4156368bd37414d
tree521f62899c442fbece55e701060256faecc111e6
parent468c6816b502614f6d5881af220f34baf72cd285
drm/i915: Clear PCODE_DATA1 on SNB+

Ville found out that the DATA1 register exists since SNB with some
scarce apparitions in the specs throughout the times. In his own words:

  Also according to Bspec the mailbox data1 register already existed
  since snb.  The hsw cdclk change sequence also mentions that it should
  be set to 0, but eg. the bdw IPS sequence doesn't mention it. I guess
  in theory some pcode command might cause it to be clobbered, so I'm
  thinking we should just explicitly set it to 0 for all platforms in
  the pcode read/write functions

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c