git.stricted.de - GitHub/LineageOS/android_kernel_motorola

author	Rajendra Nayak <rnayak@ti.com>
	Tue, 27 May 2014 08:55:43 +0000 (14:25 +0530)
committer	Tero Kristo <t-kristo@ti.com>
	Thu, 3 Jul 2014 17:59:36 +0000 (20:59 +0300)
commit	dd94324b983afe114ba9e7ee3649313b451f63ce
tree	dea1eba51a51dd520caa0e6c4ec743790788297f	tree \| snapshot (tar.gz zip)
parent	7171511eaec5bf23fb06078f59784a3a0626b38f	commit \| diff

ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates

Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000

With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000

The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>