drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variations
authorDongwon Kim <dongwon.kim@intel.com>
Thu, 14 Apr 2016 22:37:43 +0000 (15:37 -0700)
committerImre Deak <imre.deak@intel.com>
Fri, 15 Apr 2016 13:10:59 +0000 (16:10 +0300)
commitda6110bcbc0837eddf6292a0f8cb72f00507fde8
treee386b95fb81306771351ae9b438d26f03236315f
parent8f6d855c4b8a032691816723307d960a5b2c0b6d
drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variations

This patch is to correct one thing in this commit:

commit 25a56705332add0363e47b3a0eca001d6fbd5bec
Author: Dongwon Kim <dongwon.kim@intel.com>
Date:   Wed Mar 16 18:06:13 2016 -0700

    drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit

This reversed bit polarity is actually common
for all BXT and APL SoCs. Therefore, revision checking
in the original commit should be removed to make
the bit set regardless of revision ID of GFX block.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460673463-14453-1-git-send-email-dongwon.kim@intel.com
drivers/gpu/drm/i915/intel_dpll_mgr.c