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(parent: edaf3fb) | patch
clk: sunxi: add gating support to PLL1
authorEmilio López <emilio@elopez.com.ar>
Mon, 23 Dec 2013 03:32:34 +0000 (00:32 -0300)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:08:06 +0000 (17:08 -0300)
commitd838ff33ec3a6262f44476d8edc0303acdc16580
tree0c700acae95db629e0e085bc4608752e4f77b515tree | snapshot (tar.gz zip)
parentedaf3fb580df7f6c510699664f51485030a29f17commit | diff
clk: sunxi: add gating support to PLL1

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | blame | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | blame | history