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(parent: 980019d) | patch
x86, Calgary: Limit the max PHB number to 256
authorDarrick J. Wong <djwong@us.ibm.com>
Thu, 1 Jul 2010 00:45:19 +0000 (17:45 -0700)
committerH. Peter Anvin <hpa@zytor.com>
Thu, 1 Jul 2010 05:41:42 +0000 (22:41 -0700)
commitd596043d71ff0d7b3d0bead19b1d68c55f003093
tree97336d074c772c4ea7715f9fc9114f25fbfab4eatree | snapshot (tar.gz zip)
parent980019d74e4b2428362b36a0506519d6d9460800commit | diff
x86, Calgary: Limit the max PHB number to 256

The x3950 family can have as many as 256 PCI buses in a single system, so
change the limits to the maximum.  Since there can only be 256 PCI buses in one
domain, we no longer need the BUG_ON check.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
arch/x86/kernel/pci-calgary_64.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)