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(parent: aaf8a51) | patch
drm/i915: fix lane bandwidth capping for DP 1.2 sinks
authorImre Deak <imre.deak@intel.com>
Tue, 9 Jul 2013 14:05:26 +0000 (17:05 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 9 Jul 2013 14:35:50 +0000 (16:35 +0200)
commitd4eead50eb206b875f54f66cc0f6ec7d54122c28
treef94f8acf87faffa3585bd8920a0f8bd72224d2dctree | snapshot (tar.gz zip)
parentaaf8a5167291b65e9116cb8736d862965b57c13acommit | diff
drm/i915: fix lane bandwidth capping for DP 1.2 sinks

DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which
the driver will treat as an invalid value and use 1.62Gbps instead. Fix
this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw.

Also add a warning for reserved values.

v2:
- allow only bw values explicitly listed in the DP standard (Daniel,
  Chris)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c diff | blob | blame | history