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(parent: c5107b8) | patch
drm/i915: extract and improve gen8_irq_power_well_post_enable
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 4 Jul 2014 14:50:31 +0000 (11:50 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 23 Jul 2014 05:05:32 +0000 (07:05 +0200)
commitd49bdb0e1054d022cc6f88fcecf9c79bae66eab0
treedb3e2bc2ce5e819705c1ebf21e10bec934dce8adtree | snapshot (tar.gz zip)
parentc5107b875a84f0b25d1d6b8fbc9acb22440b746fcommit | diff
drm/i915: extract and improve gen8_irq_power_well_post_enable

Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_irq.c diff | blob | blame | history
drivers/gpu/drm/i915/intel_drv.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history