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ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero
authorVladimir Murzin <vladimir.murzin@arm.com>
Mon, 12 Jun 2017 12:35:52 +0000 (13:35 +0100)
committerRussell King <rmk+kernel@armlinux.org.uk>
Mon, 12 Jun 2017 14:47:29 +0000 (15:47 +0100)
commitd360a687d99577110c181e67ebfb9a1b6fed63a2
treeac764253122a5234c0c229110f0b0b065a2d8f1dtree | snapshot (tar.gz zip)
parentbbeedfda8eee0b17ea16e4e157c596095458676acommit | diff
ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero

Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
arch/arm/kernel/setup.c diff | blob | blame | history