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(parent: c9eaa44) | patch
clk: tegra: Fix PLLE programming
authorThierry Reding <treding@nvidia.com>
Fri, 4 Apr 2014 13:55:13 +0000 (15:55 +0200)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Thu, 17 Apr 2014 11:12:34 +0000 (14:12 +0300)
commitd0f02ce3b1685ef6ffe43692034599790f83e7ab
tree08b7289a4e5db66417e3d1455577345f29114ed1tree | snapshot (tar.gz zip)
parentc9eaa447e77efe77b7fa4c953bd62de8297fd6c5commit | diff
clk: tegra: Fix PLLE programming

PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | blame | history