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(parent: aa12d7a) | patch
pwm: mediatek: Fix PWM source clock selection
authorZhi Mao <zhi.mao@mediatek.com>
Fri, 30 Jun 2017 06:05:17 +0000 (14:05 +0800)
committerThierry Reding <thierry.reding@gmail.com>
Mon, 21 Aug 2017 08:39:09 +0000 (10:39 +0200)
commitcd30798a6c17c1fa182e9b0bb85bd973776ff193
tree3572bfe3bb23753643c6355852481c36e89c39bbtree | snapshot (tar.gz zip)
parentaa12d7a7a978ac5f3202cac8f2f671fd267bf5e3commit | diff
pwm: mediatek: Fix PWM source clock selection

In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
drivers/pwm/pwm-mediatek.c diff | blob | blame | history