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(parent: cbfe8fa) | patch
iommu/arm-smmu: Fix enabling of PRIQ interrupt
authorMarc Zyngier <marc.zyngier@arm.com>
Wed, 15 Jul 2015 10:55:18 +0000 (11:55 +0100)
committerWill Deacon <will.deacon@arm.com>
Fri, 31 Jul 2015 10:38:14 +0000 (11:38 +0100)
commitccd6385dfbb7b2f2e6670b5cfc55bb7ec0aa3839
treed150fda1fe2cfd5868b2c8aeb3d0de88fdb248a7tree | snapshot (tar.gz zip)
parentcbfe8fa6cd672011c755c3cd85c9ffd4e2d10a6fcommit | diff
iommu/arm-smmu: Fix enabling of PRIQ interrupt

When an ARM SMMUv3 instance supports PRI, the driver registers
an interrupt handler, but fails to enable the generation of
such interrupt at the SMMU level.

This patches simply moves the enable flags to a variable that
gets updated by the PRI handling code before being written to the
SMMU register.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/iommu/arm-smmu-v3.c diff | blob | blame | history