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powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs
authorNate Case <ncase@xes-inc.com>
Wed, 10 Jun 2009 20:37:28 +0000 (15:37 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 16 Jun 2009 02:45:30 +0000 (21:45 -0500)
commitcab888e678d0986ebce95464d3842a6aeca1e3d8
treee6ead4aac68d3a1b694c1cfed56b4650a1ab8715tree | snapshot (tar.gz zip)
parentc7a7a5b9a27e28ce5f800ead9091ce68d37e8088commit | diff
powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

Some boot loaders may not enable L1 instruction/data cache.  Check if
data and instruction caches are enabled, and enable them if needed.

Signed-off-by: Nate Case <ncase@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/include/asm/reg_booke.h diff | blob | blame | history
arch/powerpc/kernel/cpu_setup_fsl_booke.S diff | blob | blame | history