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(parent: 7e7d76c) | patch
drm/i915: enable PCH PLL, FDI training and transcoder even for eDP
authorJesse Barnes <jbarnes@virtuousgeek.org>
Fri, 10 Sep 2010 17:57:18 +0000 (10:57 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 10 Sep 2010 22:13:47 +0000 (23:13 +0100)
commitc98e9dcf9023e72837c1c01251f370e2358a0de6
tree13e1e29466c013b9b0b5adc53eda0c0830c08284tree | snapshot (tar.gz zip)
parent7e7d76c306adb73a41d2678a42a11004df2519b7commit | diff
drm/i915: enable PCH PLL, FDI training and transcoder even for eDP

eDP panels require these to be set up prior to panel power sequencing,
or they'll fail to power on due to an "asset not ready" check.  And of
course, eDP panels attached to anything other than DP_A need them
enabled regardless, since they'll be driven from the CPU through FDI out
to the PCH.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_display.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)