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(parent: beff0d0) | patch
drm/i915: Add some L3 registers to the parser whitelist
authorBrad Volkin <bradley.d.volkin@intel.com>
Tue, 17 Jun 2014 21:10:34 +0000 (14:10 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Jun 2014 22:48:35 +0000 (00:48 +0200)
commitc9224faa59c3071ecfa2d4b24592f4eb61e57069
treebc0e9d8d9155ac38644f461f1d8945f8a781e1eetree | snapshot (tar.gz zip)
parentbeff0d0f6121f6a2a818a050a1e4d91706b3f190commit | diff
drm/i915: Add some L3 registers to the parser whitelist

Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_cmd_parser.c diff | blob | blame | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history