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ARM: dts: r8a73a4: Add L2 cache-controller nodes
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 Feb 2016 20:38:29 +0000 (21:38 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 19 Feb 2016 05:52:21 +0000 (14:52 +0900)
commitc86a4b621994dbe9361185362c4be6887f04b1a4
tree55dca258775d61ba8ae37f1d1fe33306839256f6tree | snapshot (tar.gz zip)
parent57f9156bc620ac561ed46b2316de328e6b280023commit | diff
ARM: dts: r8a73a4: Add L2 cache-controller nodes

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a73a4.dtsi diff | blob | blame | history