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MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.
authorRalf Baechle <ralf@linux-mips.org>
Thu, 22 May 2014 07:55:02 +0000 (09:55 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 23 May 2014 13:12:38 +0000 (15:12 +0200)
commitc836732fa058a62bb8f30a7a03f776f6c488fa58
tree2d970152b6cf195b22088d2f7a1fe52890c92012tree | snapshot (tar.gz zip)
parent70e4c234aa48e11c0575364939dfab4cb27b2172commit | diff
MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.

R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has
data cache lines that are always 32 bytes so the call is pointless in
r4k_blast_dcache_page_dc64.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c diff | blob | blame | history