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(parent: f1dbf8e) | patch
[MIPS] Check FCSR for pending interrupts, alternative version
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Fri, 9 Mar 2007 16:03:48 +0000 (01:03 +0900)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 17 Mar 2007 01:03:25 +0000 (01:03 +0000)
commitc6a2f4679331206ef5d353fc9a6cda2fa4aef8c6
tree9634ba2d5b6c6c97f4301b28088c68254201bf74tree | snapshot (tar.gz zip)
parentf1dbf8e718ef0ddb196a28bcc71925ac7da881afcommit | diff
[MIPS] Check FCSR for pending interrupts, alternative version

Commit 6d6671066a311703bca1b91645bb1e04cc983387 is incomplete and misses
non-r4k CPUs.  This patch reverts the commit and fixes in other way.

 o Do FCSR checking in caller of restore_fp_context.
 o Send SIGFPE if the signal handler set any FPU exception bits.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/r4k_fpu.S diff | blob | blame | history
arch/mips/kernel/signal-common.h diff | blob | blame | history
arch/mips/kernel/signal.c diff | blob | blame | history
arch/mips/kernel/signal32.c diff | blob | blame | history
arch/mips/kernel/signal_n32.c diff | blob | blame | history