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ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset
authorNicolin Chen <Guangyu.Chen@freescale.com>
Wed, 23 Jul 2014 11:23:39 +0000 (19:23 +0800)
committerMark Brown <broonie@linaro.org>
Fri, 25 Jul 2014 17:52:35 +0000 (18:52 +0100)
commitc44b56af9ca3a6f135d8f22b9a240f53909b371e
tree2f21074e058c08f5eb37b4993dfee8096927967atree | snapshot (tar.gz zip)
parentf4075a8f452aff5465c6522c92da9db71ed11b7fcommit | diff
ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset

TE/RE bit of T/RCSR will remain set untill the current frame is physically
finished. The FIFO reset operation should wait this bit's totally cleared
rather than ignoring its status which might cause TE/RE disabling failed.

This patch adds delay and timeout to wait for its completion before FIFO
reset.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
sound/soc/fsl/fsl_sai.c diff | blob | blame | history