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(parent: 9ca20a8) | patch
[AVR32] Optimize the TLB miss handler
authorHaavard Skinnemoen <hskinnemoen@atmel.com>
Wed, 14 Mar 2007 12:59:13 +0000 (13:59 +0100)
committerHaavard Skinnemoen <hskinnemoen@atmel.com>
Fri, 27 Apr 2007 11:44:15 +0000 (13:44 +0200)
commitc0c3e81608fc300027f2131e351e67ab118cf24c
treed1e7ebe582e7a554a6735cb17ed0a60c6be03c09tree | snapshot (tar.gz zip)
parent9ca20a8366462c553c27216161c735937f9de108commit | diff
[AVR32] Optimize the TLB miss handler

Reorder some instructions and change the register usage to reduce
the number of pipeline stalls. Also use the bfextu and bfins
instructions for bitfield manipulations instead of shifting and
masking.

This makes gzipping a 80MB file approximately 2% faster.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
arch/avr32/kernel/entry-avr32b.S diff | blob | blame | history