ARM: EXYNOS: fix pm code to check for cortex A9 rather than the SoC
authorAbhilash Kesavan <a.kesavan@samsung.com>
Tue, 17 Jun 2014 23:08:49 +0000 (08:08 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Tue, 17 Jun 2014 23:08:49 +0000 (08:08 +0900)
commitc0c3c3590d0d178cd461f0c29aca0e83294c4bc4
tree7886e7b5a5967d04ef9bcc82b0dae4a96e53ae9e
parent1d80415db64b54141ef02ae58bd2f273d0ac3c38
ARM: EXYNOS: fix pm code to check for cortex A9 rather than the SoC

We have an soc check to ensure that the scu and certain A9 specific
registers are not accessed on Exynos5250 (which is A15 based).
Rather than adding another soc specific check for 5420 let us test
for the Cortex A9 primary part number.

This resolves the below crash seen on exynos5420 during core switching
after the CPUIdle consolidation series was merged.

[  155.975589] [<c0013174>] (scu_enable) from [<c001b0dc>] (exynos_cpu_pm_notifier+0x80/0xc4)
[  155.983833] [<c001b0dc>] (exynos_cpu_pm_notifier) from [<c003c1b0>] (notifier_call_chain+0x44/0x84)
[  155.992851] [<c003c1b0>] (notifier_call_chain) from [<c007a49c>] (cpu_pm_notify+0x20/0x3c)
[  156.001089] [<c007a49c>] (cpu_pm_notify) from [<c007a564>] (cpu_pm_exit+0x20/0x38)
[  156.008635] [<c007a564>] (cpu_pm_exit) from [<c0019e98>] (bL_switcher_thread+0x298/0x40c)
[  156.016788] [<c0019e98>] (bL_switcher_thread) from [<c003842c>] (kthread+0xcc/0xe8)
[  156.024426] [<c003842c>] (kthread) from [<c000e438>] (ret_from_fork+0x14/0x3c)
[  156.031621] Code: ea017fec c0530a00 c052e3f8 c0012dcc (e5903000

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-exynos/pm.c