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clk: tegra: Properly setup PWM clock on Tegra30
authorThierry Reding <thierry.reding@gmail.com>
Tue, 29 Oct 2013 15:51:12 +0000 (16:51 +0100)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Tue, 26 Nov 2013 16:46:57 +0000 (18:46 +0200)
commitc04bf559264de4f986463c639fabef2028542924
tree30bfdeed6283bfb603cad43a5519a09c75570dc4tree | snapshot (tar.gz zip)
parent43e36a9646ec7d0180d638c095cca36484cc6f82commit | diff
clk: tegra: Properly setup PWM clock on Tegra30

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra30.c diff | blob | blame | history