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(parent: fac12f6) | patch
drm/i915/chv: Add DPINVGTT registers defines for Cherryview
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 2 May 2014 08:35:51 +0000 (11:35 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 6 May 2014 19:17:31 +0000 (21:17 +0200)
commitbf67a6fd5ef8ef7f6a8548bc9a6441b290bf2752
treea88554c3b2c2fad9eaf5c55e8da8d4e339d39769tree | snapshot (tar.gz zip)
parentfac12f6cdcb25cac8f28818a8f9adb079575f9a0commit | diff
drm/i915/chv: Add DPINVGTT registers defines for Cherryview

Due to Pipe C DPINVGTT has more bits on CHV.

v2: Fix comment to say VLV/CHV (Rafael)

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history