MIPS: BMIPS: Align secondary boot sequence with latest firmware releases
authorKevin Cernekee <cernekee@gmail.com>
Tue, 21 Oct 2014 04:27:52 +0000 (21:27 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 24 Nov 2014 06:45:10 +0000 (07:45 +0100)
commitbdb2e05c900d0c2a14605411dc054f284241d42e
treede867f32032648094369d30993955cf5c760e9ef
parent3526f74fa925e44335b94ed0c9f93648e26058ef
MIPS: BMIPS: Align secondary boot sequence with latest firmware releases

On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register.  But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux is fully responsible for booting CPU2/CPU3.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8157/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/smp-bmips.c