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(parent: 790d929) | patch
clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
authorIcenowy Zheng <icenowy@aosc.xyz>
Tue, 13 Dec 2016 15:22:48 +0000 (23:22 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 2 Jan 2017 21:24:55 +0000 (22:24 +0100)
commitbb021cda2ccf45ee9470bf0f8c55323ad1c761ae
tree215b4d74e53bebc292329acb7046ac9e32a9e686tree | snapshot (tar.gz zip)
parent790d929b540661945d1c70652ffb602c5c06ad85commit | diff
clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-a33.c diff | blob | blame | history