drm/i915/skl: Allocate DDB portions for display planes
authorDamien Lespiau <damien.lespiau@intel.com>
Tue, 4 Nov 2014 17:06:43 +0000 (17:06 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 7 Nov 2014 17:42:05 +0000 (18:42 +0100)
commitb9cec07585cf1f554810097b8088b8e1f3f5137b
treed9e49ff1c30c2b265f06cf86ae1bb55333054c61
parent2d41c0b59afcdd87d689212cdb929709ffc27d08
drm/i915/skl: Allocate DDB portions for display planes

v2: Fix the 3rd plane/cursor logic (Pradeep Bhat)
v3: Fix one-by-one error in the DDB allocation code
v4: Rebase on top of the skl_pipe_pixel_rate() argument change
v5: Replace the available/start/end output parameters of
    skl_ddb_get_pipe_allocation_limits() by a single ddb entry constify
    a few arguments
    Make nth_active_pipe 0 indexed
    Use sizeof(variable) instead of sizeof(type)
    (Ville)
v6: Use the for_each_crtc() macro instead of list_for_each_entry()

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c