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MIPS: Octeon: Update L2 Cache code for CN63XX
authorDavid Daney <ddaney@caviumnetworks.com>
Thu, 7 Oct 2010 23:03:42 +0000 (16:03 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 29 Oct 2010 18:08:35 +0000 (19:08 +0100)
commitb8db85b5b5c22236d168eb03a67c2641bf7fa651
treea372c5f0db85255ce60f2670a1211f205239d045tree | snapshot (tar.gz zip)
parenta70b13a9f07ae0e21870ed3e9b6829f556579c5ccommit | diff
MIPS: Octeon: Update L2 Cache code for CN63XX

The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/executive/cvmx-l2c.c diff | blob | blame | history
arch/mips/include/asm/octeon/cvmx-asm.h diff | blob | blame | history
arch/mips/include/asm/octeon/cvmx-l2c.h diff | blob | blame | history
Motorola kernel-slsi