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(merge: e387088 e142a4e)
Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorMichael Turquette <mturquette@linaro.org>
Wed, 28 Jan 2015 00:26:12 +0000 (16:26 -0800)
committerMichael Turquette <mturquette@linaro.org>
Wed, 28 Jan 2015 00:26:12 +0000 (16:26 -0800)
commitb80418f3c05061094c57ad7a661c9fb14e3f8b73
treedd5d12e53b34f610a6f668504fe8ffb9ca063d3ftree | snapshot (tar.gz zip)
parente387088a03a07583f248a237cb00c5c955a394c9commit | diff
parente142a4e91443d0fc2185c821626e66729f323d1ccommit | diff
Merge tag 'v3.20-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
drivers/clk/rockchip/clk-rk3288.c diff1 | diff2 | blob | history