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(parent: a925810) | patch
clk: socfpga: Fix the smplsel on Arria10 and Stratix10
authorDinh Nguyen <dinguyen@kernel.org>
Thu, 8 Jun 2017 14:18:39 +0000 (09:18 -0500)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 20 Jun 2017 00:01:55 +0000 (17:01 -0700)
commitb7f8101d6e75fefd22c39624a30c9ed3d7a72463
tree69bc892406162ff2d5474256ac99eef0038f26e3tree | snapshot (tar.gz zip)
parenta925810f6ebb89ef94977c4f499264c8fd199dffcommit | diff
clk: socfpga: Fix the smplsel on Arria10 and Stratix10

The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.

Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.

Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/socfpga/clk-gate-a10.c diff | blob | blame | history
drivers/clk/socfpga/clk.h diff | blob | blame | history