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(parent: bf911e9) | patch
{net, ib}/mlx5: Make cache line size determination at runtime.
authorDaniel Jurgens <danielj@mellanox.com>
Tue, 25 Oct 2016 15:36:24 +0000 (18:36 +0300)
committerDavid S. Miller <davem@davemloft.net>
Sat, 29 Oct 2016 16:00:39 +0000 (12:00 -0400)
commitb47bd6ea40636362a8b6605de51207cc387ba0b8
tree6bed00d13dfefc41b5ad060358426d299f1fc0d8tree | snapshot (tar.gz zip)
parentbf911e985d6bbaa328c20c3e05f4eb03de11fdd6commit | diff
{net, ib}/mlx5: Make cache line size determination at runtime.

ARM 64B cache line systems have L1_CACHE_BYTES set to 128.
cache_line_size() will return the correct size.

Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities
handling.')
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/infiniband/hw/mlx5/main.c diff | blob | blame | history
drivers/infiniband/hw/mlx5/qp.c diff | blob | blame | history
drivers/net/ethernet/mellanox/mlx5/core/alloc.c diff | blob | blame | history
include/linux/mlx5/driver.h diff | blob | blame | history