drm/i915: BDW clock change support
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 3 Jun 2015 12:45:13 +0000 (15:45 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 12 Jun 2015 10:14:34 +0000 (13:14 +0300)
commitb432e5cfd5e92127ad2dd83bfc3083f1dbce43fb
tree2676ef799c8ed623ce083a53d6b25b0dc302ca73
parentebb72aad41e231fe5c586785dbbf5910867e7978
drm/i915: BDW clock change support

Add support for changing cdclk frequency during runtime on BDW.

Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk,
so take that into account when computing the max pixel rate.

v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
v4: Rebased to the latest
v5: Rebased to the latest
v6: Patch order shuffle so that Broadwell CD clock change is
    applied before the patch for Haswell CD clock change
v7: Fix for patch style problems

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c