drm/i915/bxt: eDP Panel Power sequencing
authorVandana Kannan <vandana.kannan@intel.com>
Thu, 18 Jun 2015 05:30:55 +0000 (11:00 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 18 Jun 2015 06:46:21 +0000 (08:46 +0200)
commitb0a08bec96318be54db97c3f0b9e37b52561f9ea
tree33bb9582e327b6959832761a2ba973db6005cbfa
parentce52299ca6ac23222e040284913d1271edc96459
drm/i915/bxt: eDP Panel Power sequencing

Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the 2 sets of registers.

v2:
[Jani] Added 2nd set of PPS registers and the macro
Jani's review comments
- remove reference in i915_suspend.c
- Use BXT PP macro
Squashing all PPS related patches into one.

v3: Jani's review comments addressed
- Use pp_ctl instead of pp
- ironlake_get_pp_control() is not required for BXT
- correct the use of && in the print statement
- drop the shift in the print statement

v4: Jani's comments
- modify ironlake_get_pp_control() - dont set unlock key for bxt

v5: Sonika's comments addressed
- check alignment
- move pp_ctrl_reg write (after ironlake_get_pp_control())
to !IS_BROXTON case.
- check before subtracting 1 for t11_t12

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dp.c