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(parent: 58a6a7d) | patch
drm/amdgpu: refine cz uvd clock gate logic.
authorRex Zhu <Rex.Zhu@amd.com>
Fri, 11 Nov 2016 03:18:07 +0000 (11:18 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Nov 2016 20:08:39 +0000 (15:08 -0500)
commitb02d4081a5260778ec9d20ac1f079c2b503d9943
treee218336ddad103867d827635c8f7b0bfee576a00tree | snapshot (tar.gz zip)
parent58a6a7dd19980087f5bbbcf7fcfc02a90b72de79commit | diff
drm/amdgpu: refine cz uvd clock gate logic.

sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/cz_dpm.c diff | blob | blame | history
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c diff | blob | blame | history