drm/i915: don't access FW_BLC_SELF on 965G
authorJesse Barnes <jbarnes@virtuousgeek.org>
Wed, 30 Jun 2010 20:49:37 +0000 (13:49 -0700)
committerEric Anholt <eric@anholt.net>
Thu, 1 Jul 2010 22:30:12 +0000 (15:30 -0700)
commitadcdbc6651a7086b99827cf50623a02d941261f1
tree91cb2cfed63506b7e37761b3b96d83f20f5a6041
parent43ed340ad93dcefe00a8f116b7e1b9dab2958543
drm/i915: don't access FW_BLC_SELF on 965G

The register offset for FW_BLC_SELF is a totally different set of bits
on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
FW_BLC_SELF on 965G chips.

Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874.

Cc: stable@kernel.org
Tested-by: Norman Yarvin <yarvin@yarchive.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/intel_display.c