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mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Tue, 6 May 2014 08:46:10 +0000 (11:46 +0300)
committerLee Jones <lee.jones@linaro.org>
Tue, 3 Jun 2014 07:11:28 +0000 (08:11 +0100)
commitac8320c471e187d7fdc90f807199ff77c116a668
tree19052d42fd12b3290a26a2d1c5f99aeba06a5d70tree | snapshot (tar.gz zip)
parenta58cc84cafa2376a2d5fcdb3d513327a2fb813c2commit | diff
mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk

When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be
put in bypass mode.
This will fix HPPLL use on boards with 19.2MHz mclk.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
drivers/mfd/twl6040.c diff | blob | blame | history