clk: at91: Fix division by zero in PLL recalc_rate()
authorRonald Wahl <rwahl@gmx.de>
Wed, 10 Oct 2018 13:54:54 +0000 (15:54 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Nov 2018 08:24:07 +0000 (09:24 +0100)
commitabe960b761eb6b3b32b099c80535b3d3943db040
tree3accecc59c0572f2c172ba9e93c8fff110023c8e
parentf074414aff064f7167756713ebdd8622592fe350
clk: at91: Fix division by zero in PLL recalc_rate()

commit 0f5cb0e6225cae2f029944cb8c74617aab6ddd49 upstream.

Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <rwahl@gmx.de>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/at91/clk-pll.c