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(parent: fc4033b) | patch
powerpc/e500mc: flush L2 on NAP for e500mc
authorKumar Gala <galak@kernel.crashing.org>
Thu, 19 Jun 2008 14:40:31 +0000 (09:40 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Thu, 26 Jun 2008 06:49:03 +0000 (01:49 -0500)
commitaba11fc50c925bbd6fb25d54eae2f86277a3b107
tree52c85a46371ca4ef05042600507ecd5bdcfa2842tree | snapshot (tar.gz zip)
parentfc4033b2f8b1482022bff3d05505a1b1631bb6decommit | diff
powerpc/e500mc: flush L2 on NAP for e500mc

If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/kernel/idle_e500.S diff | blob | blame | history
include/asm-powerpc/cputable.h diff | blob | blame | history
include/asm-powerpc/reg_booke.h diff | blob | blame | history