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ARM: cache-v7: optimise test for Cortex A9 r0pX devices
authorRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 3 Apr 2015 10:32:34 +0000 (11:32 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Tue, 14 Apr 2015 21:26:52 +0000 (22:26 +0100)
commitaaf4b5d92ce8299a363f1c0d7dc00aafde532e56
treea1cc24bf63db4e54e2fb3b528d6dd68a162a74dctree | snapshot (tar.gz zip)
parentd3cd451dfb579367b4c5968256b3d8342dd0b0e8commit | diff
ARM: cache-v7: optimise test for Cortex A9 r0pX devices

Eliminate one unnecessary instruction from this test by pre-shifting
the Cortex A9 ID - we can shift the actual ID in the teq instruction
thereby losing the pX bit of the ID at no cost.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/cache-v7.S diff | blob | blame | history