clk: uniphier: fix DAPLL2 clock rate of Pro5
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 5 Oct 2017 02:32:59 +0000 (11:32 +0900)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 14 Dec 2017 08:53:12 +0000 (09:53 +0100)
commita967ab0f7338e84d379b7a764bf446221de21d3e
tree36096a0207433a4215adf9a932ad84fb7abf0996
parentcd11ce209d73cba69a5776818795446a7991755e
clk: uniphier: fix DAPLL2 clock rate of Pro5

[ Upstream commit 67affb78a4e4feb837953e3434c8402a5c3b272f ]

The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/uniphier/clk-uniphier-sys.c