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(parent: 5ee426c) | patch
drm/i915: Implement MI decode for gen8
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Mon, 30 Jun 2014 16:53:39 +0000 (09:53 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 7 Jul 2014 21:16:34 +0000 (23:16 +0200)
commita6cdb93a7a135b853353fffecbdc2e60ba56a016
treec523639a6041e944e3d44d95bbe7ab5cb53df3catree | snapshot (tar.gz zip)
parent5ee426ca135c91e071d23853e876b957526841c5commit | diff
drm/i915: Implement MI decode for gen8

Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.

This implementation was based on Ben's work and on Ville's suggestion for Ben

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Fixup format string.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_irq.c diff | blob | blame | history
Motorola kernel-slsi